GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
Hanrui Wang1, Kuan Wang1, Jiacheng Yang1, Linxiao Shen2, Nan Sun2, Hae-Seung Lee1, Song Han1 1Massachusetts Institute of Technology 2University of Texas at Austin
Abstract
Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer
中文速览
晶体管尺寸优化（transistor sizing）是模拟电路设计中最耗时的环节之一，设计师每换一种工艺节点或电路拓扑就得几乎从头再来。本文提出 GCN-RL Circuit Designer，把电路本身当作图结构，用图卷积神经网络（Graph Convolutional Network, GCN）提取拓扑连接特征，再结合强化学习（Reinforcement Learning, RL）来自动搜索最优晶体管参数，从而把"黑箱优化"变成能理解电路结构的"开箱优化"。训练好的 RL 智能体可以直接迁移到不同工艺节点或不同电路拓扑上继续优化，大幅减少重新仿真的次数。实验表明，该方法在四种电路上的性能指标（Figure of Merit）均优于贝叶斯优化、进化算法、随机搜索及人类专家设计，而跨工艺节点和跨拓扑的迁移实验也证明了 GCN 对知识迁移不可或缺。这项工作为模拟电路设计自动化提供了一条兼顾性能与可复用性的新路径，有望显著缩短从设计到流片的周期。
原文 arXiv:2005.00406;中英对照 + 大白话阅读 https://aha.fim.ai/paper/2005.00406v1